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1/28 august 2004 m34c02 2 kbit serial i2c bus eeprom for dimm serial presence detect features summary software data protection for lower 128 bytes two wire i 2 c serial interface 100khz and 400khz transfer rates single supply voltage: ? 2.5 to 5.5v up to 400khz for m34c02-w ? 2.2 to 5.5v up to 400khz for m34c02-l ? 1.8 to 5.5v up to 100khz for m34c02-r ? 1.7 to 3.6v up to 100khz for m34c02-f byte and page write (up to 16 bytes) random and sequential read modes self-timed programming cycle automatic address incrementing enhanced esd/latch-up protection more than 1 million erase/write cycles more than 40 year data retention table 1. product list figure 1. packages reference part number m34c02 m34c02-w m34c02-l m34c02-r m34c02-f pdip8 (bn) so8 (mn) 150 mil width 8 1 tssop8 (dw) 169 mil width tssop8 (ds) 3x3mm2 body size (msop) 8 1 ufdfpn8 (mb) 2x3mm2 (mlp)
m34c02 2/28 table of contents features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 1. product list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 1. packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3. dip, so, tssop and mlp connections (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 2. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 power on reset: vcc lock-out write protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 serial clock (scl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 serial data (sda) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 chip enable (e0, e1, e2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 write control (wc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 4. maximum rl value versus bus capacitance (cbus) for an i2c bus . . . . . . . . . . . . . . . 5 figure 5. i2c bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 start condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 acknowledge bit (ack) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 4. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 6. setting the write protection register (wc = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 setting the software write-protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 7. result of setting the write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 8. write mode sequences in a non write-protected area . . . . . . . . . . . . . . . . . . . . . . . . . . 9 write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 byte write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 9. write cycle polling flowchart using ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 minimizing system delays by polling on ack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 10.read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 random address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 current address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 sequential read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 acknowledge in read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 use within a dram dimm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3/28 m34c02 programming the m34c02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 5. dram dimm connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 initial delivery state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 11.serial presence detect block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 6. absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 7. operating conditions (m34c02-w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 8. operating conditions (m34c02-l). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 9. operating conditions (m34c02-r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 10. operating conditions (m34c02-f). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 11. ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 12.ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 12. input parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 13. dc characteristics (m34c02-w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 14. dc characteristics (m34c02-l). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 15. dc characteristics (m34c02-r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 16. dc characteristics (m34c02-f) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 17. ac characteristics (m34c02-w, m34c02-l). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 18. ac characteristics (m34c02-r, m34c02-f) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 13.ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 14.pdip8 ? 8 pin plastic dip, 0.25mm lead frame, package outline . . . . . . . . . . . . . . . . . 21 table 19. pdip8 ? 8 pin plastic dip, 0.25mm lead frame, package mechanical data . . . . . . . . . . 21 figure 15.so8 narrow ? 8 lead plastic small outline, 150 mils body width, package outline . . . . 22 table 20. so8 narrow ? 8 lead plastic small outline, 150 mils body width, mechanical data . . . . 22 figure 16.ufdfpn8 (mlp8) 8-lead ultra thin fine pitch dual flat package no lead 2x3mm2, outline 23 table 21. ufdfpn8 (mlp8) 8-lead ultra thin fine pitch dual flat package no lead 2x3mm2, data . 23 figure 17.tssop8 ? 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . 24 table 22. tssop8 ? 8 lead thin shrink small outline, package mechanical data . . . . . . . . . . . . 24 figure 18.tssop8 3x3mm2 ? 8 lead thin shrink small outline, 3x3mm2 body size, outline . . . . 25 table 23. tssop8 3x3mm2 ? 8 lead thin shrink small outline, 3x3mm2 body size, data . . . . . . 25 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 24. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 25. revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
m34c02 4/28 summary description the m34c02 is a 2kbit serial eeprom memory able to lock permanently the data in its first half (from location 00h to 7fh). this facility has been designed specifically for use in dram dimms (du- al interline memory modules) with serial presence detect. all the information concerning the dram module configuration (such as its access speed, its size, its organization) can be kept write protect- ed in the first half of the memory. this bottom half of the memory area can be write- protected using a specially designed software write protection mechanism. by sending the de- vice a specific sequence, the first 128 bytes of the memory become permanently write protected. care must be taken when using this sequence as its effect cannot be reversed. in addition, the de- vice allows the entire memory area to be write pro- tected, using the wc input (for example by tieing this input to v cc ). these i 2 c-compatible electrically erasable pro- grammable memory (eeprom) devices are orga- nized as 256x8 bits. figure 2. logic diagram i 2 c uses a two wire serial interface, comprising a bi-directional data line and a clock line. the device carries a built-in 4-bit device type identifier code (1010) in accordance with the i 2 c bus definition to access the memory area and a second device type identifier code (0110) to access the protec- tion register. these codes are used together with three chip enable inputs (e2, e1, e0) so that up to eight 2kbit devices may be attached to the i2c bus and selected individually. the device behaves as a slave device in the i 2 c protocol, with all memory operations synchronized by the serial clock. read and write operations are initiated by a start condition, generated by the bus master. the start condition is followed by a device select code and rw bit (as described in table 3. ), terminated by an acknowledge bit. when writing data to the memory, the memory in- serts an acknowledge bit during the 9 th bit time, following the bus master?s 8-bit transmission. when data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. data transfers are terminated by a stop condition after an ack for write, and af- ter a noack for read. figure 3. dip, so, tssop and mlp connections (top view) note: see package mechanical section for package dimen- sions, and how to identify pin-1. table 2. signal names power on reset: v cc lock-out write protect in order to prevent data corruption and inadvertent write operations during power up, a power on re- set (por) circuit is included. the internal reset is held active until v cc has reached the por thresh- old value, and all operations are disabled ? the de- vice will not respond to any command. in the same way, when v cc drops from the operating voltage, below the por threshold value, all operations are disabled and the device will not respond to any command. a stable and valid v cc (as defined in table 7. to table 10. ) must be applied before applying any logic signal. ai01931 3 e0-e2 sda v cc m34c02 wc scl v ss e0, e1, e2 chip enable sda serial data scl serial clock wc write control v cc supply voltage v ss ground sda v ss scl wc e1 e0 v cc e2 ai01932c m34c02 1 2 3 4 8 7 6 5
5/28 m34c02 signal description serial clock (scl) this input signal is used to strobe all data in and out of the device. in applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor can be con- nected from serial clock (scl) to v cc . ( figure 4. indicates how the value of the pull-up resistor can be calculated). in most applications, though, this method of synchronization is not employed, and so the pull-up resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output. serial data (sda) this bi-directional signal is used to transfer data in or out of the device. it is an open drain output that may be wire-or?ed with other open drain or open collector signals on the bus. a pull up resistor must be connected from serial data (sda) to v cc . ( fig- ure 4. indicates how the value of the pull-up resis- tor can be calculated). chip enable (e0, e1, e2) these input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code. these inputs must be tied to v cc or v ss to establish the device select code. write control (wc ) this input signal is provided for protecting the con- tents of the whole memory from inadvertent write operations. write control (wc ) is used to enable (when driven low) or disable (when driven high) write instructions to the entire memory area or to the protection register. when write control (wc ) is tied low or left uncon- nected, the write protection of the first half of the memory is determined by the status of the protec- tion register. figure 4. maximum r l value versus bus capacitance (c bus ) for an i 2 c bus ai01665 v cc c bus sda r l master r l scl c bus 100 0 4 8 12 16 20 c bus (pf) maximum rp value (k ? ) 10 1000 fc = 400khz fc = 100khz
m34c02 6/28 figure 5. i 2 c bus protocol table 3. device select code note: 1. the most significant bit, b7, is sent first. 2. e0, e1 and e2 are compared against the respective external pins on the memory device. device type identifier 1 chip enable address 2 rw b7 b6 b5 b4 b3 b2 b1 b0 memory area select code (two arrays) 1010e2e1e0rw protection register select code 0110e2e1e0rw scl sda scl sda sda start condition sda input sda change ai00792b stop condition 1 23 7 89 msb ack start condition scl 1 23 7 89 msb ack stop condition
7/28 m34c02 device operation the device supports the i 2 c protocol. this is sum- marized in figure 5. . any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. the device that controls the data transfer is known as the bus master, and the other as the slave de- vice. a data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. the memory device is always a slave in all communication. start condition start is identified by a falling edge of serial data (sda) while serial clock (scl) is stable in the high state. a start condition must precede any data transfer command. the device continuously monitors (except during a write cycle) serial data (sda) and serial clock (scl) for a start condition, and will not re spond unless one is given. stop condition stop is identified by a rising edge of serial data (sda) while serial clock (scl) is stable and driv- en high. a stop condition terminates communica- tion between the device and the bus master. a read command that is followed by noack can be followed by a stop condition to force the device into the stand-by mode. a stop condition at the end of a write command triggers the internal ee- prom write cycle. acknowledge bit (ack) the acknowledge bit is used to indicate a success- ful byte transfer. the bus transmitter, whether it be bus master or slave device, releases serial data (sda) after sending eight bits of data. during the 9 th clock pulse period, the receiver pulls serial data (sda) low to acknowledge the receipt of the eight data bits. data input during data input, the device samples serial data (sda) on the rising edge of serial clock (scl). for correct device operation, serial data (sda) must be stable during the rising edge of serial clock (scl), and the serial data (sda) signal must change only when serial clock (scl) is driv- en low. memory addressing to start communication between the bus master and the slave device, the bus master must initiate a start condition. following this, the bus master sends the device select code, shown in table 3. (on serial data (sda), most significant bit first). the device select code consists of a 4-bit device type identifier, and a 3-bit chip enable ?address? (e2, e1, e0). to address the memory array, the 4- bit device type identifier is 1010b; to address the protection register, it is 0110b. up to eight memory devices can be connected on a single i 2 c bus. each one is given a unique 3-bit code on the chip enable (e0, e1, e2) inputs. when the device select code is received, the de- vice only responds if the chip enable address is the same as the value on the chip enable (e0, e1, e2) inputs. the 8 th bit is the read/write bit (rw ). this bit is set to 1 for read and 0 for write operations. if a match occurs on the device select code, the corresponding device gives an acknowledgment on serial data (sda) during the 9 th bit time. if the device does not match the device select code, it deselects itself from the bus, and goes into stand- by mode. table 4. operating modes note: 1. x = v ih or v il . mode rw bit wc 1 bytes initial sequence current address read 1 x 1 start, device select, rw = 1 random address read 0x 1 start, device select, rw = 0, address 1 x restart, device select, rw = 1 sequential read 1 x 1 similar to current or random address read byte write 0 v il 1 start, device select, rw = 0 page write 0 v il 16 start, device select, rw = 0
m34c02 8/28 figure 6. setting the write protection register (wc = 0) setting the software write-protection the m34c02 has a hardware write-protection fea- ture, using the write control (wc ) signal. this sig- nal can be driven high or low, and must be held constant for the whole instruction sequence. when write control (wc ) is held low, the whole memory array (addresses 00h to ffh) is write pro- tected. when write control (wc ) is held high, the write protection of the memory array is dependent on whether software write-protection has been set. software write-protection allows the bottom half of the memory area (addresses 00h to 7fh) to be permanently write protected irrespective of subse- quent states of the write control (wc ) signal. the write protection feature is activated by writing once to the protection register. the protection register is accessed with the device select code set to 0110b (as shown in table 3. ), and the e2, e1 and e0 bits set according to the states being applied on the e2, e1 and e0 signals. as for any other write command, write control (wc ) needs to be held low. address and data bytes must be sent with this command, but their values are all ignored, and are treated as don?t care. once the protec- tion register has been written, the write protection of the first 128 bytes of the memory is enabled, and it is not possible to unprotect these 128 bytes, even if the device is powered off and on, and re- gardless the state of write control (wc ). when the protection register has been written, the m34c02 no longer responds to the device type identifier 0110b in either read or write mode. figure 7. result of setting the write protection start sda line ai01935b ack word address value (don't care) ack data value (don't care) stop ack control byte bus activity master bus activity default eeprom memory area state before write access to the protect register ai01936c standard array ffh standard array 80h 7fh 00h standard array ffh write protected array 80h 7fh 00h state of the eeprom memory area after write access to the protect register memory area
9/28 m34c02 figure 8. write mode sequences in a non write-protected area write operations following a start condition the bus master sends a device select code with the rw bit reset to 0. the device acknowledges this, as shown in figure 8. , and waits for an address byte. the device re- sponds to the address byte with an acknowledge bit, and then waits for the data byte. when the bus master generates a stop condition immediately after the ack bit (in the ?10 th bit? time slot), either at the end of a byte write or a page write, the internal memory write cycle is triggered. a stop condition at any other time slot does not trigger the internal write cycle. during the internal write cycle, serial data (sda) and serial clock (scl) are ignored, and the de- vice does not respond to any requests. byte write after the device select code and the address byte, the bus master sends one data byte. if the addressed location is hardware write-protected, the device replies to the data byte with noack, and the location is not modified. if, instead, the ad- dressed location is not write-protected, the device replies with ack. the bus master terminates the transfer by generating a stop condition, as shown in figure 8. . page write the page write mode allows up to 16 bytes to be written in a single write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits are the same. if more bytes are sent than will fit up to the end of the page, a condition known as ?roll- over? occurs. this should be avoided, as data starts to become overwritten in an implementation dependent way. the bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the device if write control (wc ) is low. if the addressed loca- tion is hardware write-protected, the device replies to the data byte with noack, and the locations are not modified. after each byte is transferred, the in- ternal byte address counter (the 4 least significant address bits only) is incremented. the transfer is terminated by the bus master generating a stop condition. stop start byte write dev sel byte addr data in start page write dev sel byte addr data in 1 data in 2 ai01941 stop data in n ack ack ack r/w ack ack ack r/w ack ack
m34c02 10/28 figure 9. write cycle polling flowchart using ack minimizing system delays by polling on ack during the internal write cycle, the device discon- nects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. the maximum write time (t w ) is shown in table 17. and table 18. , but the typical time is shorter. to make use of this, a polling sequence can be used by the bus master. the sequence, as shown in figure 9. , is: ? initial condition: a write cycle is in progress. ? step 1: the bus master issues a start condition followed by a device select code (the first byte of the new instruction). ? step 2: if the device is busy with the internal write cycle, no ack will be returned and the bus master goes back to step 1. if the device has terminated the internal write cycle, it responds with an ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during step 1). write cycle in progress ai01847c next operation is addressing the memory start condition device select with rw = 0 ack returned yes no yes no restart stop data for the write operation device select with rw = 1 send address and receive ack first byte of instruction with rw = 0 already decoded by the device yes no start condition continue the write operation continue the random read operation
11/28 m34c02 figure 10. read mode sequences note: 1. the seven most significant bits of the device select code of a random read (in the 1 st and 3 rd bytes) must be identical. read operations read operations are performed independently of whether hardware or software protection has been set. the device has an internal address counter which is incremented each time a byte is read. random address read a dummy write is first performed to load the ad- dress into this address counter (as shown in fig- ure 10. ) but without sending a stop condition. then, the bus master sends another start condi- tion, and repeats the device select code, with the rw bit set to 1. the device acknowledges this, and outputs the contents of the addressed byte. the bus master must not acknowledge the byte, and terminates the transfer with a stop condition. current address read for the current address read operation, following a start condition, the bus master only sends a de- vice select code with the rw bit set to 1. the de- vice acknowledges this, and outputs the byte addressed by the internal address counter. the counter is then incremented. the bus master ter- minates the transfer with a stop condition, as shown in figure 10. , without acknowledging the byte. start dev sel * byte addr start dev sel data out 1 ai01942 data out n stop start current address read dev sel data out random address read stop start dev sel * data out sequential current read stop data out n start dev sel * byte addr sequential random read start dev sel * data out 1 stop ack r/w no ack ack r/w ack ack r/w ack ack ack no ack r/w no ack ack ack r/w ack ack r/w ack no ack
m34c02 12/28 sequential read this operation can be used after a current ad- dress read or a random address read. the bus master does acknowledge the data byte output, and sends additional clock pulses so that the de- vice continues to output the next byte in sequence. to terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a stop condition, as shown in figure 10. . the output data comes from consecutive address- es, with the internal address counter automatically incremented after each byte output. after the last memory address, the address counter ?rolls-over?, and the device continues to output data from memory address 00h. acknowledge in read mode for all read commands, the device waits, after each byte read, for an acknowledgment during the 9 th bit time. if the bus master does not drive serial data (sda) low during this time, the device termi- nates the data transfer and switches to its stand- by mode. use within a dram dimm in the application, the m34c02 is soldered directly in the printed circuit module. the 3 chip enable in- puts (pins 1, 2 and 3) are wired at v cc or v ss through the dimm socket (see table 5. ). the pull- up resistors needed for normal behavior of the i 2 c bus are connected on the i 2 c bus of the mother- board (as shown in figure 11. ). the write control (wc ) of the m34c02 can be left unconnected. however, connecting it to v ss is recommended, to maintain full read and write ac- cess. programming the m34c02 when the m34c02 is delivered, full read and write access is given to the whole memory array. it is recommended that the first step is to use the test equipment to write the module information (such as its access speed, its size, its organization) to the first half of the memory, starting from the first memory location. when the data has been validat- ed, the test equipment can send a write command to the protection register, using the device select code ?01100000b? followed by an address and data byte (made up of don?t care values) as shown in figure 6. . the first 128 bytes of the mem- ory area are then write- protected, and the m34c02 will no longer respond to the specific device select code ?0110000xb?. it is not possible to reverse this sequence. table 5. dram dimm connections initial delivery state the device is delivered with the memory array erased: all bits are set to 1 (each byte contains ffh). dimm position e2 e1 e0 0 v ss v ss v ss 1 v ss v ss v cc 2 v ss v cc v ss 3 v ss v cc v cc 4 v cc v ss v ss 5 v cc v ss v cc 6 v cc v cc v ss 7 v cc v cc v cc
13/28 m34c02 figure 11. serial presence detect block diagram note: 1. e0, e1 and e2 are wired at each dimm socket in a binary sequence for a maximum of 8 devices. 2. common clock and common data are shared across all the devices. 3. pull-up resistors are required on all sda and scl bus lines (typically 4.7 k ? ) because these lines are open drain when used as outputs. r = 4.7k ? ai01937 dimm position 7 sda scl e0 e1 e2 v cc dimm position 6 sda scl e0 e1 e2 dimm position 5 sda scl e0 e1 e2 dimm position 4 sda scl e0 e1 e2 dimm position 3 sda scl e0 e1 e2 dimm position 2 sda scl e0 e1 e2 v cc dimm position 1 sda scl e0 e1 e2 dimm position 0 sda scl e0 e1 e2 v ss v ss v ss v cc v ss v ss v cc v cc v ss v cc v cc v ss v ss v cc scl line sda line from the motherboard i 2 c master controller
m34c02 14/28 maximum rating stressing the device above the rating listed in the absolute maximum ratings" table may cause per- manent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im- plied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 6. absolute maximum ratings note: 1. compliant with jedec std j-std-020b (for small body, sn-pb or pb assembly), the st ecopack ? 7191395 specification, and the european directive on restrictions on hazardous substances (rohs) 2002/95/eu. 2. jedec std jesd22-a114a (c1=100 pf, r1=1500 ? , r2=500 ? ) symbol parameter min. max. unit t stg storage temperature ?65 150 c t lead lead temperature during soldering 1 see note 1 c v io input or output voltage ?0.50 6.5 v v cc supply voltage ?0.50 6.5 v v esd electrostatic discharge voltage (human body model) 2 ?4000 4000 v
15/28 m34c02 dc and ac parameters this section summarizes the operating and mea- surement conditions, and the dc and ac charac- teristics of the device. the parameters in the dc and ac characteristic tables that follow are de- rived from tests performed under the measure- ment conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parame- ters. table 7. operating conditions (m34c02-w) table 8. operating conditions (m34c02-l) table 9. operating conditions (m34c02-r) table 10. operating conditions (m34c02-f) symbol parameter min. max. unit v cc supply voltage 2.5 5.5 v t a ambient operating temperature ?40 85 c symbol parameter min. max. unit v cc supply voltage 2.2 5.5 v t a ambient operating temperature ?40 85 c symbol parameter min. max. unit v cc supply voltage 1.8 5.5 v t a ambient operating temperature ?40 85 c symbol parameter min. max. unit v cc supply voltage 1.7 3.6 v t a ambient operating temperature 0 70 c
m34c02 16/28 table 11. ac measurement conditions figure 12. ac measurement i/o waveform table 12. input parameters note: 1. t a = 25 c, f = 400 khz 2. sampled only, not 100% tested. symbol parameter min. max. unit c l load capacitance 100 pf input rise and fall times 50 ns input levels 0.2v cc to 0.8v cc v input and output timing reference levels 0.3v cc to 0.7v cc v symbol parameter 1,2 test condition min . max . unit c in input capacitance (sda) 8 pf c in input capacitance (other pins) 6 pf z wcl wc input impedance v in < 0.5 v 5 20 k ? z wch wc input impedance v in > 0.7v cc 500 k ? t ns pulse width ignored (input filter on scl and sda) single glitch 100 500 ns ai00825b 0.8v cc 0.2v cc 0.7v cc 0.3v cc input and output timing reference levels input levels
17/28 m34c02 table 13. dc characteristics (m34c02-w) table 14. dc characteristics (m34c02-l) symbol parameter test condition (in addition to those in table 7. ) min. max. unit i li input leakage current (scl, sda) v in = v ss or v cc 2 a i lo output leakage current v out = v ss or v cc, sda in hi-z 2 a i cc supply current v cc =5v, f c =400khz (rise/fall time < 30ns) 2ma v cc =2.5v, f c =400khz (rise/fall time < 30ns) 1ma i cc1 stand-by supply current v in = v ss or v cc , v cc = 5v 1 a v in = v ss or v cc , v cc = 2.5v 0.5 a v il input low voltage (e2, e1, e0, scl, sda) ?0.3 0.3v cc v input low voltage (wc ) ?0.3 0.5 v v ih input high voltage (e2, e1, e0, scl, sda, wc ) 0.7v cc v cc +1 v v ol output low voltage i ol = 3ma, v cc = 5v 0.4 v i ol = 2.1ma, v cc = 2.5v 0.4 v symbol parameter test condition (in addition to those in table 8. ) min. max. unit i li input leakage current (scl, sda) v in = v ss or v cc 2 a i lo output leakage current v out = v ss or v cc, sda in hi-z 2 a i cc supply current v cc =5v, f c =400khz (rise/fall time < 30ns) 2ma v cc =2.5v, f c =400khz (rise/fall time < 30ns) 1ma v cc =2.2v, f c =400khz (rise/fall time < 30ns) 1ma i cc1 stand-by supply current v in = v ss or v cc , v cc = 5 v 1 a v in = v ss or v cc , 2.2v v cc < 2.5v 0.5 a v il input low voltage (e2, e1, e0, scl, sda) ?0.3 0.3v cc v input low voltage (wc ) ?0.3 0.5 v v ih input high voltage (e2, e1, e0, scl, sda, wc ) 0.7v cc v cc +1 v v ol output low voltage i ol = 3ma, v cc = 5v 0.4 v i ol = 2.1ma, 2.2v v cc < 2.5v 0.4 v
m34c02 18/28 table 15. dc characteristics (m34c02-r) table 16. dc characteristics (m34c02-f) note: 1. preliminary data. symbol parameter test condition (in addition to those in table 9. ) min. max. unit i li input leakage current (scl, sda) v in = v ss or v cc 2 a i lo output leakage current v out = v ss or v cc, sda in hi-z 2 a i cc supply current v cc =1.8v, f c =100khz (rise/fall time < 30ns) 1ma i cc1 stand-by supply current v in = v ss or v cc , v cc = 5v 1a v in = v ss or v cc , 1.8v v cc < 2.5v 0.5 a v il input low voltage (e2, e1, e0, scl, sda) 2.5v v cc 5.5v ? 0.3 0.3 v cc v 1.8v v cc < 2.5v ? 0.3 0.25 v cc v input low voltage (wc ) ?0.3 0.5 v v ih input high voltage (e2, e1, e0, scl, sda, wc ) 0.7v cc v cc +1 v v ol output low voltage i ol = 3ma, v cc = 5v 0.4 v i ol = 2.1ma, 2.2v v cc < 2.5v 0.4 v i ol = 0.15ma, v cc = 1.8v 0.2 v symbol parameter test condition (in addition to those in table 10. ) min. 1 max. 1 unit i li input leakage current (scl, sda) v in = v ss or v cc 2 a i lo output leakage current v out = v ss or v cc, sda in hi-z 2 a i cc supply current v cc =1.7v, f c =100khz (rise/fall time < 30ns) 1ma i cc1 stand-by supply current v in = v ss or v cc , v cc = 3.6v 1 a v in = v ss or v cc , 1.7v v cc < 2.5v 0.5 a v il input low voltage (e2, e1, e0, scl, sda) 2.5v v cc 3.6v ? 0.3 0.3 v cc v 1.7v v cc < 2.5v ? 0.3 0.25 v cc v input low voltage (wc ) ?0.3 0.5 v v ih input high voltage (e2, e1, e0, scl, sda, wc ) 0.7v cc v cc +1 v v ol output low voltage i ol = 2.1ma, 2.2v v cc 3.6v 0.4 v i ol = 0.15ma, v cc = 1.7v 0.2 v
19/28 m34c02 table 17. ac characteristics (m34c02-w, m34c02-l) note: 1. for a restart condition, or following a write cycle. 2. sampled only, not 100% tested. 3. to avoid spurious start and stop conditions, a minimum delay is placed between scl=1 and the falling or rising edge of sda. table 18. ac characteristics (m34c02-r, m34c02-f) note: 1. for a restart condition, or following a write cycle. 2. sampled only, not 100% tested. 3. to avoid spurious start and stop conditions, a minimum delay is placed between scl=1 and the falling or rising edge of sda. test conditions specified in table 11. and table 7. or table 8. symbol alt. parameter min. max. unit f c f scl clock frequency 400 khz t chcl t high clock pulse width high 600 ns t clch t low clock pulse width low 1300 ns t dl1dl2 2 t f sda fall time 20 300 ns t dxcx t su:dat data in set up time 100 ns t cldx t hd:dat data in hold time 0 ns t clqx t dh data out hold time 200 ns t clqv 3 t aa clock low to next data valid (access time) 200 900 ns t chdx 1 t su:sta start condition set up time 600 ns t dlcl t hd:sta start condition hold time 600 ns t chdh t su:sto stop condition set up time 600 ns t dhdl t buf time between stop condition and next start condition 1300 ns t w t wr write time 10 ms test conditions specified in table 11. and table 9. or table 10. symbol alt. parameter min. max. unit f c f scl clock frequency 100 khz t chcl t high clock pulse width high 4000 ns t clch t low clock pulse width low 4700 ns t dl1dl2 2 t f sda fall time 20 300 ns t dxcx t su:dat data in set up time 250 ns t cldx t hd:dat data in hold time 0 ns t clqx t dh data out hold time 200 ns t clqv 3 t aa clock low to next data valid (access time) 200 3500 ns t chdx 1 t su:sta start condition set up time 4700 ns t dlcl t hd:sta start condition hold time 4000 ns t chdh t su:sto stop condition set up time 4000 ns t dhdl t buf time between stop condition and next start condition 4700 ns t w t wr write time 10 ms
m34c02 20/28 figure 13. ac waveforms scl sda in scl sda out scl sda in tchcl tdlcl tchdx start condition tclch tdxcx tcldx sda input sda change tchdh tdhdl stop condition data valid tclqv tclqx tchdh stop condition tchdx start condition write cycle tw ai00795c start condition
21/28 m34c02 package mechanical figure 14. pdip8 ? 8 pin plastic dip, 0.25mm lead frame, package outline note: drawing is not to scale. table 19. pdip8 ? 8 pin plastic dip, 0.25mm lead frame, package mechanical data symb. mm inches typ. min. max. typ. min. max. a 5.33 0.210 a1 0.38 0.015 a2 3.30 2.92 4.95 0.130 0.115 0.195 b 0.46 0.36 0.56 0.018 0.014 0.022 b2 1.52 1.14 1.78 0.060 0.045 0.070 c 0.25 0.20 0.36 0.010 0.008 0.014 d 9.27 9.02 10.16 0.365 0.355 0.400 e 7.87 7.62 8.26 0.310 0.300 0.325 e1 6.35 6.10 7.11 0.250 0.240 0.280 e2.54??0.100?? ea 7.62 ? ? 0.300 ? ? eb 10.92 0.430 l 3.30 2.92 3.81 0.130 0.115 0.150 pdip-b a2 a1 a l be d e1 8 1 c ea b2 eb e
m34c02 22/28 figure 15. so8 narrow ? 8 lead plastic small outline, 150 mils body width, package outline note: drawing is not to scale. table 20. so8 narrow ? 8 lead plastic small outline, 150 mils body width, mechanical data symb. mm inches typ. min. max. typ. min. max. a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d 4.80 5.00 0.189 0.197 e 3.80 4.00 0.150 0.157 e1.27??0.050?? h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.40 0.90 0.016 0.035 0 8 0 8 n8 8 cp 0.10 0.004 so-a e n cp b e a d c l a1 1 h h x 45?
23/28 m34c02 figure 16. ufdfpn8 (mlp8) 8-lead ultra thin fine pitch dual flat package no lead 2x3mm2, outline note: 1. drawing is not to scale. 2. the central pad (the area e2 by d2 in the above illustration) is pulled, internally, to v ss . it must not be allowed to be connected to any other voltage or signal line on the pcb, for example during the soldering process. table 21. ufdfpn8 (mlp8) 8-lead ultra thin fine pitch dual flat package no lead 2x3mm2, data symbol mm inches typ. min. max. typ. min. max. a 0.55 0.50 0.60 0.022 0.020 0.024 a1 0.00 0.05 0.000 0.002 b 0.25 0.20 0.30 0.010 0.008 0.012 d 2.00 0.079 d2 1.55 1.65 0.061 0.065 ddd 0.05 0.002 e 3.00 0.118 e2 0.15 0.25 0.006 0.010 e 0.50 ? ? 0.020 ? ? l 0.45 0.40 0.50 0.018 0.016 0.020 l1 0.15 0.006 l3 0.30 0.012 n8 8 d e ufdfpn-01 a a1 ddd l1 e b d2 l e2 l3
m34c02 24/28 figure 17. tssop8 ? 8 lead thin shrink small outline, package outline note: drawing is not to scale. table 22. tssop8 ? 8 lead thin shrink small outline, package mechanical data symbol mm inches typ. min. max. typ. min. max. a 1.200 0.0472 a1 0.050 0.150 0.0020 0.0059 a2 1.000 0.800 1.050 0.0394 0.0315 0.0413 b 0.190 0.300 0.0075 0.0118 c 0.090 0.200 0.0035 0.0079 cp 0.100 0.0039 d 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 ? ? 0.0256 ? ? e 6.400 6.200 6.600 0.2520 0.2441 0.2598 e1 4.400 4.300 4.500 0.1732 0.1693 0.1772 l 0.600 0.450 0.750 0.0236 0.0177 0.0295 l1 1.000 0.0394 0 8 0 8 tssop8am 1 8 cp c l e e1 d a2 a e b 4 5 a1 l1
25/28 m34c02 figure 18. tssop8 3x3mm2 ? 8 lead thin shrink small outline, 3x3mm2 body size, outline note: drawing is not to scale. table 23. tssop8 3x3mm2 ? 8 lead thin shrink small outline, 3x3mm2 body size, data symbol mm inches typ. min. max. typ. min. max. a 1.100 0.0433 a1 0.050 0.150 0.0020 0.0059 a2 0.850 0.750 0.950 0.0335 0.0295 0.0374 b 0.250 0.400 0.0098 0.0157 c 0.130 0.230 0.0051 0.0091 d 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 4.900 4.650 5.150 0.1929 0.1831 0.2028 e1 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 ? ? 0.0256 ? ? cp 0.100 0.0039 l 0.550 0.400 0.700 0.0217 0.0157 0.0276 l1 0.950 0.0374 0 6 0 6 tssop8bm 1 8 cp c l e e1 d a2 a e b 4 5 a1 l1
m34c02 26/28 part numbering table 24. ordering information scheme note: 1. package available only on request. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales of- fice. example: m34c02 ? w mn 6 t p device type m34 = assp i 2 c serial access eeprom device function 02 = 2 kbit (256 x 8) operating voltage w = v cc = 2.5 to 5.5v (400khz) l = v cc = 2.2 to 5.5v (400khz) r = v cc = 1.8 to 5.5v (100khz) f = v cc = 1.7 to 3.6v (100khz) package bn 1 = pdip8 mn = so8 (150 mil width) mb = udfdfpn8 (mlp8) dw = tssop8 (169 mil width) ds = tssop8 (3x3mm2 body size, msop8) device grade 6 = industrial temperature range, ?40 to 85 c. device tested with standard test flow 1 = temperature range 0 to 70 c. device tested with standard test flow option blank = standard packing t = tape and reel packing plating technology blank = standard snpb plating p = lead-free and rohs compliant g = lead-free, rohs compliant, sb 2 o 3 -free and tbba-free
27/28 m34c02 revision history table 25. revision history date rev. description of revision 27-dec-1999 2.0 adjustments to the formatting. 0 to 70c temperature range removed from dc and ac tables. no change to description of device, or parameters 07-dec-2000 2.1 new definition of lead soldering temperature absolute rating for certain packages 13-mar-2001 2.2 -r voltage range added 18-jul-2002 2.3 tssop8 (3x3mm2 body size) package (msop8) added 22-may-2002 2.4 vfdfpn8 package (mlp8) added 21-jul-2003 3.0 document reformatted. -f voltage range added. 17-mar-2004 4.0 table of contents added. mlp package changed. absolute maximum ratings for v io (min) and v cc (min) changed. soldering temperature information clarified for rohs compliant devices. device grade information clarified 14-apr-2004 5.0 typos corrected in ordering information example 26-aug-2004 6.0 device grade clarified. product list summary table added
m34c02 28/28 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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